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Altera_Forum's avatar
Altera_Forum
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13 years ago

Newbie Verilog Math Q

From my reading, it appears that a register is a 2s complement signed value. Is this correct? In other words, is the following accurate (please correct if not): reg [31:0] reg1; reg [31...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Thanks Chris....

One q regarding the statement, "Anyway the interpretation of register content as a 2-complement signed value or rather a unsigned value is a matter of your system."

Does this mean that I can select registers as signed/unsigned in Quartus. Or are you referring to my specific implementation? Could I bother you to elaborate?

ME