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Altera_Forum
Honored Contributor
Honored ContributorNewbie Verilog Math Q
From my reading, it appears that a register is a 2s complement signed value. Is this correct? In other words, is the following accurate (please correct if not): reg [31:0] reg1; reg [31...
Altera_ForumHonored Contributor
Honored ContributorThanks much. After a little more RTFM, it looks like:
reg [31:0] reg1 is unsigned reg signed [31:0] reg 2 is signed Learning on the fly is always fun..... Thnx again..
