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Honored Contributor
Honored ContributorNewbie help required ref MAX II
Hi Everyone
I'm a complete newbie when it comes to CPLD's. I've been programming PIC's for years but CPLD's are new to me and i would very much appreciate some help to get me started, thank you :) Here's me questions : 1. My first question is regarding the CLK. I mainly wish to use a MAX II as a multiplexer, routing 8 bit wide data signals to and from each other, basically sending 8 bits from here to there and then form here to over there and so on, from inputs to outputs and visa versa. The data signals will be changing state at a speed of 16Mhz but the signals will only be fowarded through the Max II to assigned outputs. Do i need to CLK the max II to do this? If not, would i need a CLK if i was to store data at an output latch? 2. My second question is regarding a counter : I need to create a 20 bit wide syncronous binary counter to address some sram. The CLK speed will be 16Mhz max. Do i inject this CLK signal into a simple assigned input pin or would it be better to inject this signal into the dedicated CLK inputs on the Max II? The CLK signal will be in bursts and the idea is to code the program to count when it see's the clk signal. 3. Third and final question : Lets say i have 8 bits connected to 8 assigned inputs, can i send these 8 bits to any assigned output pins on any bank or is it more complicated than that? I apologise for all the questions but after reading the literature some for days now, i just cannot find the answers to the above. Using the Max II as a multiplexer to just route signals looks simple but thought i'd ask the true experts :) Many thanks for your time. RonUK11 Replies
Altera_ForumQuestion 1:
You don't need a clock if you're just going to use combinatory logic or assynchronous sequential logic (latches). But problably you'll be unable to meet the timmings of your 16 MHz bus with just combinatory logic. Latches are supported but... I don't any experience with designing with latches but the general consensus is to avoid them as much as possible, at least in FPGAs/CPLDs. You should use synchronous logic (ie, registers) as much as possible. And for those, you need a proper clock signal. I presume your 16 MHz bus has an associated clock, I suggest you use it. 2. As much as possible, use the dedicated clock pins for clocks. This way, the clock signal can be routed though the FPGA using the low skew global networks. 3. There are no restrictions there.
