Newbie help required ref MAX II

Question 1:

You don't need a clock if you're just going to use combinatory logic or assynchronous sequential logic (latches).

But problably you'll be unable to meet the timmings of your 16 MHz bus with just combinatory logic. Latches are supported but... I don't any experience with designing with latches but the general consensus is to avoid them as much as possible, at least in FPGAs/CPLDs.

You should use synchronous logic (ie, registers) as much as possible. And for those, you need a proper clock signal.

I presume your 16 MHz bus has an associated clock, I suggest you use it.

2. As much as possible, use the dedicated clock pins for clocks. This way, the clock signal can be routed though the FPGA using the low skew global networks.

3. There are no restrictions there.