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Altera_Forum's avatar
Altera_Forum
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14 years ago

need some VHDL code help

I am trying to program my board so when you press the ARM and Launch button it will start up my motor.

The code not done yet, but I am stuck on getting the counter to work.

here what I have so far. 


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity launcher is
port (
      clk   : in std_logic;
        Abort : in BIT;
        ARM    : in BIT;
        Launch: in BIT;
        q     : BUFFER INTERGER RANGE 0 TO 11;
        onesegment7 : out std_logic_vector(14 downto 0));  -- 7 bit decoded output.
end launcher;
--'a' corresponds to MSB of segment7 and g corresponds to LSB of segment7.
architecture Behavioral of launcher is
begin
process (clk,bcd)
BEGIN
    IF (Abortd = '1') THEN          
        q <= 0;
        ELSIF (Launch'EVENT AND ARM='1') THEN   -- negative clock
            q <= q+1                                                  --inputs equation
case  q is
when '0000'=> onesegment7 <="000000001111110";  -- '0'
when '0001'=> onesegment7 <="000000000110000";  -- '1'
when '0010'=> onesegment7 <="000000001101101";  -- '2'
when '0011'=> onesegment7 <="000000001111001";  -- '3'
when '0100'=> onesegment7 <="000000000110011";  -- '4'
when '0101'=> onesegment7 <="000000001011011";  -- '5'
when '0110'=> onesegment7 <="000000001011111";  -- '6'
when '0111'=> onesegment7 <="000000001110000";  -- '7'
when '1000'=> onesegment7 <="000000001111111";  -- '8'
when '1001'=> onesegment7 <="000000001111011";  -- '9'
when '1010'=> onesegment7 <="001100001111110";  -- '10'
when '1111'=> onesegment7 <="100011101110111";  -- 'LA'
 --nothing is displayed when a number more than 9 is given as input.
when others=> onesegment7 <="011111111111111";
end case;
else
end if;
end process;
end Behavioral;

here the errors i get 

Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
    Info: Version 11.1 Build 173 11/01/2011 SJ Full Version
    Info: Processing started: Sat Feb 11 16:03:28 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off launcher -c launcher
Warning (20028): Parallel compilation is not licensed and has been disabled
Error (10500): VHDL syntax error at launcher.vhd(26) near text "case";  expecting ";"
Error (10500): VHDL syntax error at launcher.vhd(29) near text "when";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement
Error (10500): VHDL syntax error at launcher.vhd(30) near text "when";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement
Error (10500): VHDL syntax error at launcher.vhd(31) near text "when";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement
Error (10500): VHDL syntax error at launcher.vhd(32) near text "when";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement
Error (10500): VHDL syntax error at launcher.vhd(33) near text "when";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement
Error (10500): VHDL syntax error at launcher.vhd(34) near text "when";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement
Error (10500): VHDL syntax error at launcher.vhd(35) near text "when";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement
Error (10500): VHDL syntax error at launcher.vhd(36) near text "when";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement
Error (10500): VHDL syntax error at launcher.vhd(37) near text "when";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement
Error (10500): VHDL syntax error at launcher.vhd(38) near text "when";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement
Error (10500): VHDL syntax error at launcher.vhd(40) near text "when";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement
Error (10500): VHDL syntax error at launcher.vhd(41) near text "case";  expecting "if"
Info (12021): Found 0 design units, including 0 entities, in source file launcher.vhd
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 13 errors, 1 warning
    Error: Peak virtual memory: 408 megabytes
    Error: Processing ended: Sat Feb 11 16:03:29 2012
    Error: Elapsed time: 00:00:01
    Error: Total CPU time (on all processors): 00:00:01
Error (293001): Quartus II Full Compilation was unsuccessful. 15 errors, 1 warning

Thank you for all your help

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Alot of times one error can possibly be the cause of another, so its best to just tackle one at a time. For your first error, the statement q <= q+1 is missing the ; which is causing the error. Fix that, then I'm guessing the messages will be different.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    Alot of times one error can possibly be the cause of another, so its best to just tackle one at a time. For your first error, the statement q <= q+1 is missing the ; which is causing the error. Fix that, then I'm guessing the messages will be different.

    --- Quote End ---

    thank you, not sure how i missed that one.

    here the new errors 

    Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
    Info: Version 11.1 Build 173 11/01/2011 SJ Full Version
    Info: Processing started: Sat Feb 11 16:32:41 2012
    Info: Version 11.1 Build 173 11/01/2011 SJ Full Version
    Info: Processing started: Sat Feb 11 16:32:41 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off launcher -c launcher
Warning (20028): Parallel compilation is not licensed and has been disabled
Error (10500): VHDL syntax error at launcher.vhd(27) near text "'";  expecting "(", or an identifier, or  unary operator
Error (10500): VHDL syntax error at launcher.vhd(28) near text "'";  expecting "(", or an identifier, or  unary operator
Error (10500): VHDL syntax error at launcher.vhd(29) near text "'";  expecting "(", or an identifier, or  unary operator
Error (10500): VHDL syntax error at launcher.vhd(30) near text "'";  expecting "(", or an identifier, or  unary operator
Error (10500): VHDL syntax error at launcher.vhd(31) near text "'";  expecting "(", or an identifier, or  unary operator
Error (10500): VHDL syntax error at launcher.vhd(32) near text "'";  expecting "(", or an identifier, or  unary operator
Error (10500): VHDL syntax error at launcher.vhd(33) near text "'";  expecting "(", or an identifier, or  unary operator
Error (10500): VHDL syntax error at launcher.vhd(34) near text "'";  expecting "(", or an identifier, or  unary operator
Error (10500): VHDL syntax error at launcher.vhd(35) near text "'";  expecting "(", or an identifier, or  unary operator
Error (10500): VHDL syntax error at launcher.vhd(36) near text "'";  expecting "(", or an identifier, or  unary operator
Error (10500): VHDL syntax error at launcher.vhd(37) near text "'";  expecting "(", or an identifier, or  unary operator
Error (10500): VHDL syntax error at launcher.vhd(38) near text "'";  expecting "(", or an identifier, or  unary operator
Info (12021): Found 0 design units, including 0 entities, in source file launcher.vhd
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 12 errors, 1 warning
    Error: Peak virtual memory: 408 megabytes
    Error: Processing ended: Sat Feb 11 16:32:42 2012
    Error: Elapsed time: 00:00:01
    Error: Total CPU time (on all processors): 00:00:01
    Error: Peak virtual memory: 408 megabytes
    Error: Processing ended: Sat Feb 11 16:32:42 2012
    Error: Elapsed time: 00:00:01
    Error: Total CPU time (on all processors): 00:00:01
Error (293001): Quartus II Full Compilation was unsuccessful. 14 errors, 1 warning
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I believe the case values 0000,0001 etc, should be enclosed in "'s as in "0000", 0001", not the way you have it, '0000' '0001', the ' operator deals with single bits, the " operator deals with multiple bits. You have it right on values being loaded in onesegment7.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    q : BUFFER INTERGER RANGE 0 TO 11;

    --- Quote End ---

    should be

    q : BUFFER INTEGER RANGE 0 TO 11;

    --- Quote Start ---

    q <= q+1 --inputs equation

    --- Quote End ---

    should be

    q <= q+1; --inputs equation

    --- Quote Start --- 

     
process (clk,bcd)
BEGIN
    IF (Abortd = '1') THEN          
    ...

    --- Quote End ---

    should be 

     
process (clk,bcd)
BEGIN
    if rising_edge(clk) then -- Assuming rising edge
      IF (Abortd = '1') THEN
      ...
    end if; -- Don't forget to add one more end if to match the added 'if rising_edge(clk)

    --- Quote Start ---

    case q is

    when '0000'=> onesegment7 <="000000001111110"; -- '0'

    when '0001'=> onesegment7 <="000000000110000"; -- '1'

    etc.

    --- Quote End ---

    should be

    case q is

    when 0 => onesegment7 <="000000001111110"; -- '0'

    when 1 => onesegment7 <="000000000110000"; -- '1'

    etc.

    Kevin Jennings
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    wow thank you for all your help, I almost have it now i think.

    here is my new code 

    LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY countdownflying IS
    PORT(
       clk   : in std_logic;
        Abort : in BIT;
        ARM   : in BIT;
        Launch: in BIT;
        q : BUFFER INTEGER RANGE 0 TO 11;
        twosegment7                  : out std_logic_vector(14 downto 0));
END countdownflying;
ARCHITECTURE arc OF countdownflying IS
BEGIN
    PROCESS (clk,ARM,Abort)
    BEGIN
        IF (ARM='0' OR Abort='1') THEN
            q <= 0;
            ELSIF (clk'EVENT AND clk='0') THEN
                q <=q-1;
                case  q is
when 0 => twosegment7 <="000000001111110"; -- '0'
when 1 => twosegment7 <="000000000110000"; -- '1'
when 2 => twosegment7 <="000000001101101";  -- '2'
when 3 => twosegment7 <="000000001111001";  -- '3'
when 4 => twosegment7 <="000000000110011";  -- '4'
when 5 => twosegment7 <="000000001011011";  -- '5'
when 6 => twosegment7 <="000000001011111";  -- '6'
when 7 => twosegment7 <="000000001110000";  -- '7'
when 8 => twosegment7 <="000000001111111";  -- '8'
when 9 => twosegment7 <="000000001111011";  -- '9'
when 10 => twosegment7 <="001100001111110";  -- '10'
when 11 => twosegment7 <="100011101110111";  -- 'LA'
 --nothing is displayed when a number more than 9 is given as input.
when others=> twosegment7 <="011111111111111";
end case;
else
        END IF;
        
    END PROCESS;
END arc;

    It still showing me numbers above 11, not sure why.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    The biggest part now that I can not seem to figure out, is how do I get it to count down on it own when I press one button.

    I know my DEVRY eSOC II board has 3 built in clock, but none of them do anything when it set them to the input of my clk.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    The biggest part now that I can not seem to figure out, is how do I get it to count down on it own when I press one button.

    --- Quote End ---

    That isn't a VHDL problem, I think.

    --- Quote Start ---

    It still showing me numbers above 11, not sure why.

    --- Quote End ---

    What's your expectation for code behaviour with q = 0? An integer range 0 to 11 synthesizes as unsigned[3 downto 0]. Decrementing from 0 rolls over to 15. You need to handle the behaviour for q= 0 explicitely, whatever you want, either roll over to 11, or stop decrementing. 

    IF q = 0 THEN
   q <= ...
ELSE
   q <= q - 1;
END IF;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    That isn't a VHDL problem, I think.

    What's your expectation for code behaviour with q = 0? An integer range 0 to 11 synthesizes as unsigned[3 downto 0]. Decrementing from 0 rolls over to 15. You need to handle the behaviour for q= 0 explicitely, whatever you want, either roll over to 11, or stop decrementing. 

    IF q = 0 THEN
   q <= ...
ELSE
   q <= q - 1;
END IF;

    --- Quote End ---

    Thank you

    I got my VHDL code done now, here it is if you like to take a look. 

    LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY countdownflying IS
    PORT(
       clk   : in std_logic;
        Abort : in BIT;
        ARM   : in BIT;
        Launch: in BIT;
        Launchpress :BUFFER INTEGER RANGE 90 TO 91;
        q : BUFFER INTEGER RANGE 0 TO 15;
        red : BUFFER INTEGER RANGE 0 TO 255;
        green : BUFFER INTEGER RANGE 0 TO 255;
        twosegment7                  : out std_logic_vector(14 downto 0));
END countdownflying;
ARCHITECTURE arc OF countdownflying IS
BEGIN
    PROCESS (clk,ARM,Abort)
    BEGIN
        if (Launch='1') THEN
            Launchpress <= 91;
            end if;
    case ARM is
    when '0' =>
            q <= 11;
            red <= 0;
            green <= 0;
            twosegment7 <="000000000000000"; -- 'none'
    when '1' =>
                 red <= 255;
        case Launchpress is
            when 90 =>
    IF (Abort='1') THEN
            Launchpress <= 90;
            q <= 11;
            red <= 0;
            green <= 0;
            twosegment7 <="000000000000000"; -- 'none'
            end if;
    when 91 =>
        IF (Abort='1') THEN
            Launchpress <= 90;
            q <= 11;
            red <= 0;
            green <= 0;
            twosegment7 <="000000000000000"; -- 'none'
            ELSIF (clk'EVENT AND clk='0') THEN
            if (q <=11) THEN
                q <=q-1;
                case  q is
when 00 => twosegment7 <="100011101110111";  -- 'LA'
            green <= 0;
when 01 => twosegment7 <="000000001111110";  -- '0'
            green <= 0;
when 02 => twosegment7 <="000000000110000";  -- '1'
            green <= 1;
when 03 => twosegment7 <="000000001101101";  -- '2'
            green <= 3;
when 04 => twosegment7 <="000000001111001";  -- '3'
            green <= 7;
when 05 => twosegment7 <="000000000110011";  -- '4'
            green <= 15;
when 06 => twosegment7 <="000000001011011";  -- '5'
            green <= 31;
when 07 => twosegment7 <="000000001011111";  -- '6'
            green <= 63;
when 08 => twosegment7 <="000000001110000";  -- '7'
            green <= 127;
when 09 => twosegment7 <="000000001111111";  -- '8'
            green <= 255;
when 10 => twosegment7 <="000000001111011";  -- '9'
            green <= 255;
when 11 => twosegment7 <="001100001111110";  -- '10'
            green <= 255;
when 12 => twosegment7 <="100011101110111";  -- 'LA'
            green <= 0;
when 13 => twosegment7 <="100011101110111";  -- 'LA'
            green <= 0;
when 14 => twosegment7 <="100011101110111";  -- 'LA'
            green <= 0;
when 15 => twosegment7 <="100011101110111";  -- 'LA'
            green <= 0;
end case;
end if;
else
    END IF;
        END case;
          end case;
    END PROCESS;
END arc;

    I just need to learn how to use the on-board 24 MHZ oscillator. to control my count down by the seconds.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    You need a clock divider, using it's result as an enable signal for the slow action: 

      SIGNAL clkcnt: INTEGER RANGE 0 to 240000000-1;
...
    ELSIF (clk'EVENT AND clk='0') THEN
      IF (clkcnt < 240000000-1 THEN
        clkcnt <= clkcnt + 1;
      ELSE
        clkcnt <= 0;   
        if (q <=11) THEN
        ....
      END;
    END;

    You have various asynchronous conditions taking precedence over the synchronous process part. This is O.K. for an initial reset, but most likely not suitable for external events. You may observe unexpected behaviour like getting the q count set to illegal values due to timing violations. A state of the art synchronous design would evaluate external events in the clock edge sensitive process part, after registering the events by synchronizer FFs.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I want to thank you all for all your help.

    After hitting my head on the wall for hours, I found it best to start over and re write my code from a fresh start. With your help my new code works flawlessly and better then I had hope for.

    My code job is to control a rocket launch. The board has one ARM switch that has to be on for anything else to work. The board then has 2 blue buttons, what either one is pressed it will start the count down, but if any of the 4 red buttons are hit. The program stops what it doing and resets everything.

    My output of twosegment7 is set up like this

    "000000000000000"; The last 0 controls the rocket launch signal that goes to my bread board.

    "000000000000000"; These 0's control the first digit of the 7 segment display.

    "000000000000000"; These 0's control the second digit of the 7 segment display.

    Check out my new fully working code below 

    LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_signed.ALL;
ENTITY flyingsaucer IS
        PORT
        (
        CLK                                :IN std_logic;
        ARM,LAUNCH,LAUNCH2,ABORT    :IN std_logic;
        ABORT1,ABORT2,ABORT3            :IN std_logic;
        op,LUNCHBUTTON                    :BUFFER std_logic;
        red                                :BUFFER INTEGER RANGE 0 TO 255;
        green                             :BUFFER INTEGER RANGE 0 TO 255;
        twosegment7                        :out std_logic_vector(14 downto 0)
        );
END flyingsaucer;
ARCHITECTURE BLASTOFF of flyingsaucer IS
CONSTANT max_count: natural :=24000000;
SIGNAL count: integer;
SIGNAL counter: integer;
BEGIN
onesec : PROCESS(CLK,ARM,LAUNCH,ABORT)
            VARIABLE counter : natural RANGE 0 to max_count;
            VARIABLE count : natural;
        BEGIN
case ARM is
    when '0' =>
            red <= 0;
            green <= 0;
            twosegment7 <="000000000000000"; -- 'none'
            counter := 0;
            op <='0';
            count :=15;
            LUNCHBUTTON <= '0';
    when '1' =>
case  ABORT or ABORT1 or ABORT2 or ABORT3 is
    when '1' =>
            red <= 0;
            green <= 0;
            twosegment7 <="000000000000000"; -- 'none'
            counter := 0;
            op <='0';
            count :=15;
            LUNCHBUTTON <= '0';
    when '0' =>
        red <= 255;
            if (LAUNCH='1' OR LAUNCH2= '1') THEN
            LUNCHBUTTON <= '1';
            end if;
        IF (LUNCHBUTTON = '0') THEN
            twosegment7 <="001100001111110";  -- '10'
            counter := 0;
            op <='0';
            count :=15;
        ELSIF rising_edge(CLK) THEN
        IF counter < max_count/2 THEN
            op <='0';
                counter := counter +1;
        ELSIF counter < max_count THEN
            op<='0';
            counter :=counter +1;
        ELSE
            counter :=0;
            op <='1';
        END IF;
    IF LUNCHBUTTON = '1' THEN
    if (op = '1') THEN
    if (count = 15) THEN
            twosegment7 <="001100001111110";  -- '10'
                    count := count -1;
                    green <= 255;
    ELSIF (count = 14) THEN
            twosegment7 <="000000001111011";  -- '9'
                    count := count -1;
                    green <= 255;
    ELSIF (count = 13) THEN
            twosegment7 <="000000001111111";  -- '8'
                    count := count -1;
                    green <= 255;
    ELSIF (count = 12) THEN
            twosegment7 <="000000001110000";  -- '7'
                    count := count -1;
                    green <= 127;
    ELSIF (count = 11) THEN
            twosegment7 <="000000001011111";  -- '6'
                    count := count -1;
                    green <= 63;
    ELSIF (count = 10) THEN
            twosegment7 <="000000001011011";  -- '5'
                    count := count -1;
                    green <= 31;
    ELSIF (count = 9) THEN
            twosegment7 <="000000000110011";  -- '4'
                    count := count -1;
                    green <= 15;
    ELSIF (count = 8) THEN
            twosegment7 <="000000001111001";  -- '3'
                    count := count -1;
                    green <= 7;
    ELSIF (count = 7) THEN
            twosegment7 <="000000001101101";  -- '2'
                    count := count -1;
                    green <= 3;
    ELSIF (count = 6) THEN
            twosegment7 <="000000000110000";  -- '1'
                    count := count -1;
                    green <= 1;
    ELSIF (count = 5) THEN
            twosegment7 <="100000001111110";  -- '0'
                    count := count -1;
                    green <= 0;
    ELSIF (count = 4) THEN
            twosegment7 <="000000000000000";  -- ' . '
                    count := count -1;
                    green <= 255;
    ELSIF (count = 3) THEN
            twosegment7 <="100011101110111";  -- 'LA'
                    count := count -1;
                    green <= 0;
    ELSIF (count = 2) THEN
            twosegment7 <="000000000000000";  -- ' . '
                    count := count -1;
                    green <= 255;
    ELSIF (count = 1) THEN
            twosegment7 <="100011101110111";  -- 'LA'
                    count := count -1;
                    green <= 0;
    ELSIF (count = 0) THEN
            twosegment7 <="000000000000000";  -- ' . '
                    count := count -1;
                    green <= 0;
    END IF;
        END IF;
            END IF;
                END IF;
                    END CASE;
                        END CASE;
    END PROCESS;
END BLASTOFF;