need some VHDL code help

wow thank you for all your help, I almost have it now i think.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY countdownflying IS
    PORT(
       clk   : in std_logic;
        Abort : in BIT;
        ARM   : in BIT;
        Launch: in BIT;
        q : BUFFER INTEGER RANGE 0 TO 11;
        twosegment7                  : out std_logic_vector(14 downto 0));
END countdownflying;
ARCHITECTURE arc OF countdownflying IS
BEGIN
    PROCESS (clk,ARM,Abort)
    BEGIN
        IF (ARM='0' OR Abort='1') THEN
            q <= 0;
            ELSIF (clk'EVENT AND clk='0') THEN
                q <=q-1;
                case  q is
when 0 => twosegment7 <="000000001111110"; -- '0'
when 1 => twosegment7 <="000000000110000"; -- '1'
when 2 => twosegment7 <="000000001101101";  -- '2'
when 3 => twosegment7 <="000000001111001";  -- '3'
when 4 => twosegment7 <="000000000110011";  -- '4'
when 5 => twosegment7 <="000000001011011";  -- '5'
when 6 => twosegment7 <="000000001011111";  -- '6'
when 7 => twosegment7 <="000000001110000";  -- '7'
when 8 => twosegment7 <="000000001111111";  -- '8'
when 9 => twosegment7 <="000000001111011";  -- '9'
when 10 => twosegment7 <="001100001111110";  -- '10'
when 11 => twosegment7 <="100011101110111";  -- 'LA'
 --nothing is displayed when a number more than 9 is given as input.
when others=> twosegment7 <="011111111111111";
end case;
else
        END IF;
        
    END PROCESS;
END arc;