need some VHDL code help

You need a clock divider, using it's result as an enable signal for the slow action:

  SIGNAL clkcnt: INTEGER RANGE 0 to 240000000-1;
...
    ELSIF (clk'EVENT AND clk='0') THEN
      IF (clkcnt < 240000000-1 THEN
        clkcnt <= clkcnt + 1;
      ELSE
        clkcnt <= 0;   
        if (q <=11) THEN
        ....
      END;
    END;

You have various asynchronous conditions taking precedence over the synchronous process part. This is O.K. for an initial reset, but most likely not suitable for external events. You may observe unexpected behaviour like getting the q count set to illegal values due to timing violations. A state of the art synchronous design would evaluate external events in the clock edge sensitive process part, after registering the events by synchronizer FFs.