need help in changing the deay in SYSRESET block in Igloo-2 device implementation

Delays are not synthesizable in Verilog/VHDL. Typically when you need some sort of delay you either pipeline the signal or use counters to create functional (synthesizable) delays in hardware. I google searched "Replacing delay in synthesizable RTL" and quite a few hits looked like they would be good examples for you to take a look at.

Also you could probably ditch that SYSRESET block if all it does is deglitch a reset signal, there has to be thousands of examples on the web using filters/counters that you could replace it with and not need to deal with encrypted RTL.

Hi,

thanks for ur reply.

in Igloo2 device it is recommended to use SYSRESET block to deglitch the reset signal.

SYSRESET block is generating reset output if and only if input reset is active for minimum 10ps.In my board v want to consider the reset as valid only if it is active for 500ps.so finding out ways to change the deglitch parameter

I haven't used VHDL in a long time but if that delay is stored as a generic (I think that's what VHDL calls parameters) then when you instantiate their block you should be able to set the generic to whatever you want. If that value is actually a delay and not synthesizeable it won't matter what you set it to, and given the IP is encrypted the only way to find out what it implements is through trial and error I guess. If you are stuck for more than 30 minutes I recommend just looking around for a reset deglitch block from somewhere, there has to be thousands of them only a google search away that are plain text and not encrypted.

A deglitch block is literally a counter so worst comes to worst it only takes a minute to type one up in HDL.

In simulation whr i need to give compiled libraries,v are compiling verilog file which is in installed directory inwhich code is as below for SYSRESET block.Its not generic to pass whr it is being instantiated.If i change delay here and compile able to see effect in simulation.

`timescale 1 ps/1 ps

module SYSRESET(input DEVRST_N,

output POWER_ON_RESET_N);

reg reset_n_int;

initial begin

reset_n_int = 1'b1;

# 1;

reset_n_int = 1'b0;

# 1000;

reset_n_int = 1'b1;

end

and U0 ( POWER_ON_RESET_N, DEVRST_N, reset_n_int );

specify

specparam tpdLH_A_to_Y = (10:10:10);

specparam tpdHL_A_to_Y = (10:10:10);

(DEVRST_N => POWER_ON_RESET_N ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );

endspecify

endmodule

doubt is how to tell this changed delay to implementation

Thanks in advance

I don't know VHDL very well anymore but I doubt this can be synthesized:

initial begin

reset_n_int = 1'b1;

# 1;

reset_n_int = 1'b0;

# 1000;

reset_n_int = 1'b1;

end

Just because HDL simulates does not necessarily mean that it is synthesizable. If you are targeting the FPGA then you need HDL that can be synthesized if you want to see the functionality you intend.