need help in changing the deay in SYSRESET block in Igloo-2 device implementation

In simulation whr i need to give compiled libraries,v are compiling verilog file which is in installed directory inwhich code is as below for SYSRESET block.Its not generic to pass whr it is being instantiated.If i change delay here and compile able to see effect in simulation.

`timescale 1 ps/1 ps

module SYSRESET(input DEVRST_N,

output POWER_ON_RESET_N);

reg reset_n_int;

initial begin

reset_n_int = 1'b1;

# 1;

reset_n_int = 1'b0;

# 1000;

reset_n_int = 1'b1;

end

and U0 ( POWER_ON_RESET_N, DEVRST_N, reset_n_int );

specify

specparam tpdLH_A_to_Y = (10:10:10);

specparam tpdHL_A_to_Y = (10:10:10);

(DEVRST_N => POWER_ON_RESET_N ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y );

endspecify

endmodule

doubt is how to tell this changed delay to implementation

Thanks in advance