Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

need help in changing the deay in SYSRESET block in Igloo-2 device implementation

Hi, in one of our project we are using igloo2 device in which we are using "SYSRESET" block for reset deglitching.by default the out put delay is set to 10ps in the library,by chaning the veril...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I don't know VHDL very well anymore but I doubt this can be synthesized:

initial begin

reset_n_int = 1'b1;

# 1;

reset_n_int = 1'b0;

# 1000;

reset_n_int = 1'b1;

end

Just because HDL simulates does not necessarily mean that it is synthesizable. If you are targeting the FPGA then you need HDL that can be synthesized if you want to see the functionality you intend.