need help in changing the deay in SYSRESET block in Igloo-2 device implementation

Delays are not synthesizable in Verilog/VHDL. Typically when you need some sort of delay you either pipeline the signal or use counters to create functional (synthesizable) delays in hardware. I google searched "Replacing delay in synthesizable RTL" and quite a few hits looked like they would be good examples for you to take a look at.

Also you could probably ditch that SYSRESET block if all it does is deglitch a reset signal, there has to be thousands of examples on the web using filters/counters that you could replace it with and not need to deal with encrypted RTL.