Forum Discussion
Need help : implement Gigabit Ethernet
Hello,
I'm new on this forum, so I hope that I'll be clear with my question. I'm currently working on Cyclone III FPGA Development Kit with the EP3C120F780C7N. For my project I have to etablish a communication between my PC and my board with the Gigabit Ethernet. I have to send to the board datas to configure a camera and then send the pixels to the PC for a display. My PHY device is Marvell 88E1111 so I try since two weeks to configure it with RGMII interface. My problem is that I don't know how to use the TripleSpeedEthernet 9.1 either with MegaWizard Plug-In Manager (how to link all the I/O) or with SOPC (where I'm a total beginner). Can someone help me and explain me how to use these functions or how to begin (maybe a tutorial exists with v9.1sp1) to advance in my project ? Thanks in advance.36 Replies
- Altera_Forum
Honored Contributor
hinanotabu86
Maybe it would be easy to implement send and receive functions on MAC level? All you need is TSE+it's components. Besides I have workable drivers for rx\tx and i can attach it here. - Altera_Forum
Honored Contributor
about the licence, the messige is this one :
"Can't open Signal Tap II Logic Analyzer. Verify that the licence file exists and is stored in the correct location. If you are using Quartus II Web Edition Software, you must turn on the Talkback feature to use the Signal Tap II Logic Analyzer." about my licence, i get one from altera and followed all the step to use it when i try to enable signal tap, i have to choose a signal tap file, of course i haven't got one because i can't create a new one due to the previous message in the info box, and before i have turned on the talkback feature - Altera_Forum
Honored Contributor
ok ty, i'll try tis today
yesterday night i found something and tried it but it was impossible to compile the programm the link is : http://www.altera.com/support/kdb/solutions/rd11122009_293.html - Altera_Forum
Honored Contributor
You can try and debug the software and put breakpoints in the TCP/IP stack to find out what is happening but it will be more difficult than using signaltap in my opinion.
What license problems do you have? If it is just because of the Opencore evaluation window, you can start the Quartus programmer as a separate application instead of configuring the FPGA directly from Qaurtus. That way you can keep the Opencore window open and run Signaltap from Quartus. - Altera_Forum
Honored Contributor
so now i have tried with both, and still without success
about signaltap, i can't use it because a problem of licence here is what the console displays me : nios2-terminal: connected to hardware target using JTAG UART on cable nios2-terminal: "USB-Blaster [USB-0]", device 1, instance 0 nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate) =============== Software License Reminder ================ This software project uses an unlicensed version of the NicheStack TCP/IP Network Stack - Nios II Edition. If you want to ship resulting object code in your product, you must purchase a license for this software from Altera. For information go to: "http://www.altera.com/nichestack" ===================================================== InterNiche Portable TCP/IP, v3.1 Copyright 1996-2008 by InterNiche Technologies. All rights reserved. prep_tse_mac 0 Your Ethernet MAC address is 00:07:ed:ff:3b:14 prepped 1 interface, initializing... [tse_mac_init] INFO : TSE MAC 0 found at address 0x10022800 INFO : PHY Marvell 88E1111 found at PHY address 0x12 of MAC Group[0] INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0] INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link... INFO : PHY[0.0] - Auto-Negotiation PASSED INFO : PHY[0.0] - Checking link... INFO : PHY[0.0] - Link established INFO : PHY[0.0] - Speed = 1000, Duplex = Full OK, x=0, CMD_CONFIG=0x00000000 MAC post-initialization: CMD_CONFIG=0x0400020b [tse_sgdma_read_init] RX descriptor chain desc (1 depth) created mctest init called IP address of et1 : 192.168.1.234 Created "Inet main" task (Prio: 2) Created "clock tick" task (Prio: 3) DHCP timed out, going back to default IP address(es) Simple Socket Server starting up [sss_task] Simple Socket Server listening on port 30 Created "simple socket server" task (Prio: 4) then i tried a ping to 192.168.1.234 : unsuccessfull or telnet 192.168.1.234 30 : unsuccessfull any idea is welcome thanks for your help - Altera_Forum
Honored Contributor
It can be anyone of those, the PHY chip if capable of swithcing the TX/RX lines if necessary.
Did you try to find the packets with signalTap? - Altera_Forum
Honored Contributor
i continue to try by changing some Ip but unsuccessful, i have a stupid question but about the wire : is it a straight or a crossover one ?
- Altera_Forum
Honored Contributor
The message you have in wireshark is the ARP request. The PC doesn't know your board's mac address yet, so it is broadcasting the Ethernet packet (but the destination MAC should be ff:ff:ff:ff:ff:ff, not zeroes...)
If you don't get any reply, it can be for two reasons: [list][*]the TCP/IP stack doesn't receive the ARP request [*]it receives it and send a reply, but this reply isn't received by the PC[/list] It can have multiple causes, you could start by putting signaltap probes on the MII interface, and between the MAC and SGDMAs, to see if anything is going on over there. - Altera_Forum
Honored Contributor
so i'm still having this problem, i set my own ip adress for the pc as follow
192.168.1.17 255.255.255.0 192.168.1.1 and for my board as follow : 192.168.1.234 255.255.255.0 192.168.1.1 i launch wireshark before perfoming everything with nios 2 ide, and i see nothing with wireshark although my two leds (Rx and Tx) twinkle note : in wireshark, it is written that "who has 192.168.1.234 tells 192.168.1.17" without response but when i look more in details, i can see the mac adress for the destination and the source, it is ok for the source (the mac adress of my pc) but i have only 00:00:00:00:00:00 for the destination but i know that it should be the one the console in nios 2 ide gave me so 00:07:ed:ff:3b:14 any idea how i can proceed ? thanks in advance - Altera_Forum
Honored Contributor
It may be a good idea to disable the automatic IP addressing through DHCP on your PC and set up both IP addresses manually so that they are on the same subnet. The example you give should work.