Native PHY LTD and LTR Switch

hi,

attached is the sequence i am using switching from LTR to LTD.

in the example attached there are 3 bursts of data (first one at sample -528, second in -269 and a third at -125).

time period of each sample is ~3nS (311MHz clock).

the problem can be seen in the third burst:

the Native PHY managed to lock on the preamble pattern - the rx_parallel_data AAAAAAAA (sample -108) but after that the rx_parallel_data is 0x1977B9AA (sample -92) and 0x3E1461A1 (sample -91) when it should be 0x1977B9AA and 0xBE1469A1.

it looks like the problem is not the preamble length, because in case the bursts are not so close in time, there is no problem.

seems like the problem is the amount of time that the Native PHY digital reset is changing from '1' to '0' (switching from LTR to LTD).

i will need someone to help me solve this.

thanks,

Oren

hi,

can anyone help with this one?

Oren

Hi Oren,

I am Farabi who will be supporting your request.

May I know few things of your setup:

1. What kind of reset controller you used? custom logic or using Transceiver PHY reset controller IP ?

2. transceiver reconfiguration mode details.

regards,
Farabi

Hi Oren,

I am still working with engineering to confirm the issue at our side. I will update you once we have conclusion for this issue.

regards,
Farabi

Hi Oren,

based on the 3 bursts you implemented on Stratix V GX, we come into a conclusion where the shortest burst is limited to the RX deserialization factor which shown in table below :

1st burst :

2nd burst :

3rd burst ("rx_digitalreset" signal shortest period):

RX deserialization latency in Stratix V devices:

what you can do is to prolong the "rx_digitalreset" signal so that it will allow sometime for the RX deserialization block to function properly. That is why you see the "rx_set_locktodata" signal is asserted but the parallel data is not deserialized correctly, especially when changing from LTR to LTD.

regards,
Farabi