Native PHY LTD and LTR Switch

hi,

attached is the sequence i am using switching from LTR to LTD.

in the example attached there are 3 bursts of data (first one at sample -528, second in -269 and a third at -125).

time period of each sample is ~3nS (311MHz clock).

the problem can be seen in the third burst:

the Native PHY managed to lock on the preamble pattern - the rx_parallel_data AAAAAAAA (sample -108) but after that the rx_parallel_data is 0x1977B9AA (sample -92) and 0x3E1461A1 (sample -91) when it should be 0x1977B9AA and 0xBE1469A1.

it looks like the problem is not the preamble length, because in case the bursts are not so close in time, there is no problem.

seems like the problem is the amount of time that the Native PHY digital reset is changing from '1' to '0' (switching from LTR to LTD).

i will need someone to help me solve this.

thanks,

Oren