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OLevy1's avatar
OLevy1
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Native PHY LTD and LTR Switch

hi, i am using the StratixV GX Native PHY in Rx Mode to receive ONU Bursts (the same way the OLT in NGPON2 Network - chrome-extension://efaidnbmnnnibpcajpcglclefindmkaj/viewer.html?pdfurl=https%3A%...
OLevy1's avatar
OLevy1
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Thanks Farabi,

I don't really understand:

the 'rx_digital_reset' signal between 2nd and 3rd bursts is '1' for 83 clocks (311MHz), 250nS.

shouldn't it be enough?

Oren

Farabi_Altera's avatar
Farabi_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Oren,

If your design can't set rx_digital_reset longer than 250ns, due to hardware limitation, you can reduce the bit width of the FPGA fabric interface width from 32bits to 16bits to shorten the data deserialization time.

regards,
Farabi

  • Farabi_Altera's avatar
    Farabi_Altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi Oren,

    I am transferring this case to community support. If you have new question, feel free to open a new thread to get support from Intel. Otherwise, the community users will continue to help you on this thread. Thank you.

    regards,
    Farabi