Forum Discussion
Occasional ContributorNative PHY LTD and LTR Switch
Regular ContributorHi Oren,
based on the 3 bursts you implemented on Stratix V GX, we come into a conclusion where the shortest burst is limited to the RX deserialization factor which shown in table below :
1st burst :
2nd burst :
3rd burst ("rx_digitalreset" signal shortest period):
RX deserialization latency in Stratix V devices:
what you can do is to prolong the "rx_digitalreset" signal so that it will allow sometime for the RX deserialization block to function properly. That is why you see the "rx_set_locktodata" signal is asserted but the parallel data is not deserialized correctly, especially when changing from LTR to LTD.
regards,
Farabi
Occasional ContributorThanks Farabi,
I don't really understand:
the 'rx_digital_reset' signal between 2nd and 3rd bursts is '1' for 83 clocks (311MHz), 250nS.
shouldn't it be enough?
Oren
- Farabi_Altera
Hi Oren,
If your design can't set rx_digital_reset longer than 250ns, due to hardware limitation, you can reduce the bit width of the FPGA fabric interface width from 32bits to 16bits to shorten the data deserialization time.
regards,
Farabi- Farabi_Altera
Hi Oren,
I am transferring this case to community support. If you have new question, feel free to open a new thread to get support from Intel. Otherwise, the community users will continue to help you on this thread. Thank you.
regards,
Farabi
