Forum Discussion
New ContributorMy verilog code work in stimulation but not working in hardware
Hi,
project source files are incomplete, e.g. many missing modules, e.g. max21_param, counter, comparator_equal, buffer, thus can't check the design.
Notice that you don't have a testbench for top level design, without simulating the full design succesfully you can't claim that it simulates o.k.
A possible source of hardware-to-simulation mismatch is the use of ripple clocks clk_0_5s and clk 1s that may cause timing failure. Better use one system clock (50 MHz clock) together with low frequency clock enable pulses.
Super ContributorHi,
project source files are incomplete, e.g. many missing modules, e.g. max21_param, counter, comparator_equal, buffer, thus can't check the design.
Notice that you don't have a testbench for top level design, without simulating the full design succesfully you can't claim that it simulates o.k.
A possible source of hardware-to-simulation mismatch is the use of ripple clocks clk_0_5s and clk 1s that may cause timing failure. Better use one system clock (50 MHz clock) together with low frequency clock enable pulses.
MooQZThank you I have solved my problem by changing another clk_div. I didn't upload the other sources file and test bench code cuz here got 10 file upload limit, sorry for the incomplete of source file.- FvMGood that you solved the issue. Instead of appending multiple source files send .zip or project .qar.
