multiplier delay of embedded multiplier

Synthesis will do the same latency as your RTL. So if you don't have any registers, it will be purely combinatorial. If you have one at the end, it will probably suck that one into the embedded block. With your HDL open in Quartus II, go to Edit -> Insert Template -> VHDL/Verilog and there should be some good multiplier examples.

Hi Rysc,

Nios does it's own thing, and if the RTL has five levels of registers, then it will take that long. The actual embedded multiplier doesn't have 5 pipeline registers in it, so some of those will be for other logic(look at the Cyclone II handbook to see what is really built into the block). Synthesis must always match your code, the key is trying to write code that takes advantage of what's in the hardware. As long as you're inferring the blocks, you should be good.

We need to separate the idea of registers in RTL and those inside mult block.

Cyclone II doesn't have an internal pipe. I think on Stratix devices the "internal pipe" is between the multiplier and the adder, but not inside. The one I would be curious about is building the wider mults, like a 36x36 or 54x54, which stitches together the smaller mult units. I'm sure there's a way to do this, but not sure how easily it is inferred. At some point the arithmetic is best done with the megawizard to get a controlled implementation. For example, I had a case of a simple multiplier where I didn't need the adder(this was Stratix IV). Synthesis kept putting the output register after the bypassed adder, where I needed it before the adder(or vice versa, I can't remember). I ended up having to use the megawizard to craft the implementation to meet timing.

Yeah,

somewhat offtopic, but the V families are supposed to support HDL inferring of (almost) all DSP block modes. i imagine this will include internal pipelines