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Yeah,
When i was exlporing the option of adding the multiplier using the megawizard it throws out the option asking for pipeling, latency etc.... but what i wanted to know is that if I just put a multiply symbol ( *) in my vhdl code, i read in the altera documentation that the embedded multiplier is instantiated without any pipelining, but since it is 16x16 multiplication ( which is formed by joining the small blocks like 9x9), will this combinational circuit have a delay of more than a clock cycle in my case 20 ns.
Thanks,
Joseph
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zero pipeline means no delay of registering. You expect output to be ready but delayed only "through combinatorial logic" which should be well below your clock period otherwise the design will fail badly from logic delays.
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