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Altera_Forum
Honored Contributor
14 years agoSynthesis will do the same latency as your RTL. So if you don't have any registers, it will be purely combinatorial. If you have one at the end, it will probably suck that one into the embedded block. With your HDL open in Quartus II, go to Edit -> Insert Template -> VHDL/Verilog and there should be some good multiplier examples.