multiplier delay of embedded multiplier

Hi Rysc,

Thanks for your prompt reply. When i was going through the Nios II Core Implementation document, it is mentioned that for the Nios II/f core, the embedded multiplier can be included for multiplication and the cycles for the mul/muli instruction which used the embedded multiplier is 5 cycles for 32x16 multiplication, so i was thinking that the 16x16 might also take more than one cycle or the combinatorial delay could be more than 20 ns (1/50Mhz the clock freq of the SoC). Any idea on this?

Thanks,

Joseph