multiplexed display system

Your problem is here:

else if rising_edge (slow_clk) then count_2b <= count_2b +1;

it should be:

elsif rising_edge (slow_clk) then count_2b <= count_2b +1;

This should fix the first of your compile issues. (you have more, but I will leave you to them)

Now that we have that fixed, I noticed you are using a gated clock. :evil: Gated clocks should be avoided if possible. Instead use clock enables. They look something like this:

process (rst,clk)
begin
    IF (rst = '1') THEN
        count =(OTHERS => '0');
        slow_clock_enable_s <= '0';
    ELSIF rising_edge(clk) THEN
        IF (count(15) = '1') THEN
            count =(OTHERS => '0');
            slow_clock_enable_s <= '1';
        ELSE
            count <= count +1;
            slow_clock_enable_s <= '0';
        END IF;
    end if;
end process;
process (rst, clk)
begin
    if rst = '1' then 
        count_2b <= "00";
    elsif rising_edge (clk) then 
        IF (slow_clock_enable_s = '1') THEN
            count_2b <= count_2b +1;
        END IF;
    end if;
end process; 

thank you for your help,

before I see the Gated clocks and how should it be, I corrected the first problem as you said, but I got the following error in the same line of the correction (your mentioned) the error message is:

Error (10500): VHDL syntax error at multi_display_system.vhd(59) near text "rising_edge"; expecting "(", or "'", or "."

would you please show me your kind answer?

thank you

Ahh, my fault - try:

rising_edge(clk)

instead of

rising_edge (clk)

Sorry about that. I was trying to preserve your code format and didn't notice.

--- Quote Start ---

Ahh, my fault - try:

rising_edge(clk)

instead of

rising_edge (clk)

Sorry about that. I was trying to preserve your code format and didn't notice.

--- Quote End ---

I appreciate your effort to help me, thank you very much, now, the problem is the same. I put here the code after your guide:

library IEEE;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity multi_display_system is port (

rst, clk : in std_logic;

d7s : out std_logic_vector (7 downto 0);

An : out std_logic_vector (3 downto 0)

);

end multi_display_system;

architecture mixed of multi_display_system is

signal addr_bin : std_logic_vector (3 downto 0);

signal count_2b : std_logic_vector (1 downto 0);

signal count : std_logic_vector (24 downto 0);

signal slow_clk : std_logic;

begin

process (count_2b)

begin

case count_2b is

when "00" => addr_bin <= "0000";

when "01" => addr_bin <= "1001";

when "10" => addr_bin <= "1010";

when "11" => addr_bin <= "1111";

when others => null;

end case;

end process;

d7s <= "11000000" when addr_bin = "0000" else

"11111001" when addr_bin = "0001" else

"10100100" when addr_bin = "0010" else

"10110000" when addr_bin = "0011" else

"10011001" when addr_bin = "0100" else

"10010010" when addr_bin = "0101" else

"10000010" when addr_bin = "0110" else

"11111000" when addr_bin = "0111" else

"10000000" when addr_bin = "1000" else

"10010000" when addr_bin = "1001" else

"10001000" when addr_bin = "1010" else

"10000011" when addr_bin = "1011" else

"11000110" when addr_bin = "1100" else

"10100001" when addr_bin = "1101" else

"10000110" when addr_bin = "1110" else

"10001110";

process (clk,count)

begin --rising_edge(clk)

if rising_edge(clk) then count <= count +1;

end if;

-- the frequency of slow_clk is 1.49 Hz for clk = 50 MHz (50 M / 2^16 Hz = 762.94)

-- slow_clk <= count(15) ; -- display without flicker

end process;

process (rst, slow_clk)

begin

if rst = '1' then count_2b <= "00";

else if rising_edge(slow_clk) then count_2b <= count_2b +1;

end if;

end process;

process (count_2b)

begin

case count_2b is

when "00" => AN <= "1110"; -- Lights only display 0

when "01" => AN <= "1101"; -- Lights only display 0

when "10" => AN <= "1011"; -- Lights only display 0

when "11" => AN <= "0111"; -- Lights only display 0

when others => null;

end case;

end process;

end mixed;

by the way: how do you put the code in this forum using a scrolling text box?

You still haven't changed the "else if" to "elsif".

With "else if", you in fact have two nested ifs in your code, that would require two "end if;" to properly close them.

Using identation with tabs can show this:

process (rst, slow_clk)
  if rst = '1' then
    count_2b <= "00";
  else
    if rising_edge(slow_clk) then
      count_2b <= count_2b +1;
    end if;
  end if;
end process;

or

process (rst, slow_clk)
  if rst = '1' then
    count_2b <= "00";
  elsif rising_edge(slow_clk) then
    count_2b <= count_2b +1;
  end if;
end process;