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Altera_Forum
Honored Contributor
13 years agomultiplexed display system
Dear Friends, I am designing a multiplexed display system, I did the code without (as I think) errors but I got a syntax error messages as follows: library IEEE; use ieee.std_logic_1164.all...
Altera_Forum
Honored Contributor
13 years agoYour problem is here:
else if rising_edge (slow_clk) then count_2b <= count_2b +1; it should be: elsif rising_edge (slow_clk) then count_2b <= count_2b +1; This should fix the first of your compile issues. (you have more, but I will leave you to them) Now that we have that fixed, I noticed you are using a gated clock. :evil: Gated clocks should be avoided if possible. Instead use clock enables. They look something like this:
process (rst,clk)
begin
IF (rst = '1') THEN
count =(OTHERS => '0');
slow_clock_enable_s <= '0';
ELSIF rising_edge(clk) THEN
IF (count(15) = '1') THEN
count =(OTHERS => '0');
slow_clock_enable_s <= '1';
ELSE
count <= count +1;
slow_clock_enable_s <= '0';
END IF;
end if;
end process;
process (rst, clk)
begin
if rst = '1' then
count_2b <= "00";
elsif rising_edge (clk) then
IF (slow_clock_enable_s = '1') THEN
count_2b <= count_2b +1;
END IF;
end if;
end process;