Multicycle Constraint

1) The hold check is correct and should be negative. Note that a negative hold check makes timing easier to make, as you want your data delay(minus clk skew) to be longer than the hold check. In this example, there is a phase shift on the latch clock. So when the launch clock at time 10ns sends data, the setup check is that it gets their before the latching clock at time 12ns and after time 2ns, i.e. it must be shorter than 2ns and longer than -8ns.

2) The figure above it, although the lines don't exactly match up. Note that the setup and hold checks are over time. In essence, every transfer over time is checked. That's why, if you have two unrelated clocks, the setup check might be tens of thousands of ns later in time. That's because it does thousands of checks before finding the most restrictive setup.

I posted a .ppt on this forum that goes over setup and hold and multicycles:

http://www.alteraforum.com/forum/showthread.php?t=1845&highlight=timing

Personally, I think it's a lot easier, as it's less equations and more conceptual. Most importantly, don't bury yourself in understanding the guide. You have some circuit where you should know what the setup and hold requirements should be(if you don't know what you want, TimeQuest can't help you. TQ is not for helping you figure it out, it's for allowing you to tell the fitter and timing sign-off how the circuit works). Anyway, just make up some multicycle setup and hold values and see what analysis you get. Tweak them until it returns what you want. (Note that multicycles ONLY affect the launch and latch edge of an analysis, and nothing else...) So that's all you need to look at.

Rysc, i am just a beginner in timing analysis. I have some question on ur explaination.

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i.e. it must be shorter than 2ns and longer than -8ns.

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q: What does that means?

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Note that the setup and hold checks are over time. In essence, every transfer over time is checked. That's why, if you have two unrelated clocks, the setup check might be tens of thousands of ns later in time. That's because it does thousands of checks before finding the most restrictive setup

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q: If it is unrelated(exclusive to each other), the analyzer will do setup check on each clk? The path should be cut off right? Besides, is the attachment is related or unrelated?

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I posted a .ppt on this forum that goes over setup and hold and multicycles:

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I have read the .ppt. something i need ur explaination to further my understanding.

Question:

1. What does that means by 0ns, negative or positive hold time requirement? It seems to be different to the hold slack.

My Question on timing analysis

scenario:

I have a register clock with 100*clk.However, my enable signal is based on the clk. from i understand, the setup requirement is 100. On the other side, I have seen a lot of example on set it to N(setup)-1 where i dono the reason. I wish to know the reason behind it and not just blind following. FYI, I have tried set to N-2 and it fails. I totally have no idea on how to set the hold requirement and how is the impact of hold requirement.

Ur simple and details explanation would be much appreciated.

thanks a lot