Rysc, i am just a beginner in timing analysis. I have some question on ur explaination.
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i.e. it must be shorter than 2ns and longer than -8ns.
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q: What does that means?
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Note that the setup and hold checks are over time. In essence, every transfer over time is checked. That's why, if you have two unrelated clocks, the setup check might be tens of thousands of ns later in time. That's because it does thousands of checks before finding the most restrictive setup
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q: If it is unrelated(exclusive to each other), the analyzer will do setup check on each clk? The path should be cut off right? Besides, is the attachment is related or unrelated?
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I posted a .ppt on this forum that goes over setup and hold and multicycles:
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I have read the .ppt. something i need ur explaination to further my understanding.
Question:
1. What does that means by 0ns, negative or positive hold time requirement? It seems to be different to the hold slack.
My Question on timing analysis
scenario:
I have a register clock with 100*clk.However, my enable signal is based on the clk. from i understand, the setup requirement is 100. On the other side, I have seen a lot of example on set it to N(setup)-1 where i dono the reason. I wish to know the reason behind it and not just blind following. FYI, I have tried set to N-2 and it fails. I totally have no idea on how to set the hold requirement and how is the impact of hold requirement.
Ur simple and details explanation would be much appreciated.
thanks a lot