Multi Port front end IP for the single port DDR4 memory controller - Stratix10 TX

Hi amol,

We don't provide the MPFE IP core for Stratix 10 devices.

You may create a MPFE-like design using the bridge and interconnect logic in Platform Designer.

For example, if multiple FPGA modules need to access the same EMIF IP , you need an EMIF IP and multiple Avalon Memory Mapped Pipeline Bridges in Platform Designer.

The bridges can be connected to the EMIF IP through a master.

The interconnect logic will be handle by Platform Designer.

The FPGA modules then can connect to slave of the bridges.

Regards,

Adzim