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amolkumar's avatar
amolkumar
Icon for New Contributor rankNew Contributor
8 days ago

Multi Port front end IP for the single port DDR4 memory controller - Stratix10 TX

Part 1ST085EN2F43I2LGAS

Do we have IP core details or reference design for the Multi Port front end IP for the single port DDR4 memory controller. 

What we need is one external memory and EMI shared with multiple FPGA modules as shown below.

 

 

 

We need the multi-port front end IP that will enable multiple FPGA modules to access a common external memory. Do we have solution here.

Regards

amol

 

Programmable Logic Device

2 Replies

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    6 days ago

    Hi amol,

     

    We don't provide the MPFE IP core for Stratix 10 devices.

    You may create a MPFE-like design using the bridge and interconnect logic in Platform Designer.

     

    For example, if multiple FPGA modules need to access the same EMIF IP , you need an EMIF IP and multiple Avalon Memory Mapped Pipeline Bridges in Platform Designer.

    The bridges can be connected to the EMIF IP through a master.

    The interconnect logic will be handle by Platform Designer.

    The FPGA modules then can connect to slave of the bridges.

     

    Regards,

    Adzim