Multi channel for filter

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Hi,

I have implanted a multichannel fir filter using cascaded rams. These rams works as a filter delay line for a particular channel. Its working fine as far as simulation is concerned but during synthesis I m having timing errors between the o/p of a ram to the input of following ram. I have experienced that double registering the o/p of ram eases timing but in that case the cascaded rams won't behave like a single cycle delay unit.

Can anybody suggest me the architecture of a multichannel for filter that would perform better then the above mentioned arch.

Thanks

Ali umair

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Firstly,why haven't you used fir compiler (or dsp builder) and you are done in hours.

Secondly, normally I would have thought delay lines are implemented in registers(shift) but can be moved to rams(ram based shift if it supports single stage taps) to save registers.

Many modern dsp blocks support transposed and systolic structures that fit the dsp block entirely and do not need ram or fabric.

so how did you implement shift in rams? How did you get single stage taps for your stream?

I told in the initial post that I implemented delay line by connecting rams I.e. o/p of one ram is feed to the second ram. Suppose you need an 8 channel for filter having 6 taps.. So you need 6 rams conmected as mentioned and the depth of each ram would be 8. For a particular channel, we place channel number on the address fields. In. This way our rams behave like delay line. For another channel, we can simpy change the address field on all rams.

Systolic arch implemented using DSPs only is for single channel, as far as I know.

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I told in the initial post that I implemented delay line by connecting rams I.e. o/p of one ram is feed to the second ram. Suppose you need an 8 channel for filter having 6 taps.. So you need 6 rams conmected as mentioned and the depth of each ram would be 8. For a particular channel, we place channel number on the address fields. In. This way our rams behave like delay line. For another channel, we can simpy change the address field on all rams.

Systolic arch implemented using DSPs only is for single channel, as far as I know.

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Any filter structure used for single channel can be extended to multiple channels.

Anyway, you haven't mentioned your structure (not delay line but computation structure and I assume it is direct form). In this case you can put as many registers on ram data as you like provided all data lines are equally delayed. This way your filter will see stages arriving all delayed by same latency.