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Hi,
I have implanted a multichannel fir filter using cascaded rams. These rams works as a filter delay line for a particular channel. Its working fine as far as simulation is concerned but during synthesis I m having timing errors between the o/p of a ram to the input of following ram. I have experienced that double registering the o/p of ram eases timing but in that case the cascaded rams won't behave like a single cycle delay unit.
Can anybody suggest me the architecture of a multichannel for filter that would perform better then the above mentioned arch.
Thanks
Ali umair
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Firstly,why haven't you used fir compiler (or dsp builder) and you are done in hours.
Secondly, normally I would have thought delay lines are implemented in registers(shift) but can be moved to rams(ram based shift if it supports single stage taps) to save registers.
Many modern dsp blocks support transposed and systolic structures that fit the dsp block entirely and do not need ram or fabric.
so how did you implement shift in rams? How did you get single stage taps for your stream?
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