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SSmit7's avatar
SSmit7
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5 years ago

Mulitple MSI support in Cyclone IV - IP Compiler for PCI Express

Hi there I would like to implement multiple MSI using the IP compiler for PCIe, with the target device being a Cyclone IV. I have successfully managed to do this already with a Cyclone V (using...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
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5 years ago

Hi,

I choose a random OPN for Cyclone IV, the MSI capability is available.

Thanks

Best regards,

KhaiY

SSmit7's avatar
SSmit7
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5 years ago

Hello there

Thank you for the reply.

I should have been clearer: We are using a EP4CGX30CF23I7N. This device requires a soft-ip implementation. The FPGA is intended to be the endpoint, with a processor acting as the root-port. Additionally, we require an Avalon-MM interface, where the IP compiler that you show seems to require an Avalon-ST implementation. Specifically, we are implementing it in Qsys (Quartus 13.0.1). Is this possible to implement multiple MSI in that configuration?

Regards,

SS