ModelSim vsim-3039 fatal error

Modelsim simulates SystemVerilog just fine.

What's with the D:/... in the error message? That doesn't look like a valid source file.

This thread has some SystemVerilog code, you could try that

http://www.alteraforum.com/forum/showthread.php?t=34391

Cheers,

Dave

dwh,

the full line in question is:

# ** Fatal: (vsim-3039) D:/1AlteraDsgn/Quart11/0SysVerilog/CombRepeater/CombRepeaterTF.sv(5): Instantiation of 'CombRepeater' failed.

It contains the path to my design, I considered it not important.

Jaromir Kolouch

The error message tells you the problem: Instantiation of 'CombRepeater' failed.

Have you compiled the source for 'CombRepeater'?

Cheers,

Dave

Dave,

I have launched the Fitter (Place & Route) in the Task pane of Quartus GUI, passed OK, then I launched EDA Netlist Writer, and then Tools => Run EDA Simulation Tool => EDA Gate Level Simulation..., all of the Quartus GUI. I believe the Quartus ensures proper setting of ModelSim, here is corresponding part of the ModelSim log - I guess it shows all necessary:

# vcom -93 -work work {CombRepeater.vho}# Model Technology ModelSim ALTERA vcom 6.6d Compiler 2010.11 Nov 2 2010# -- Loading package standard# -- Loading package std_logic_1164# -- Loading package vital_timing# -- Loading package vital_primitives# -- Loading package cycloneiv_atom_pack# -- Loading package cycloneiv_components# -- Compiling entity combrepeater# -- Compiling architecture structure of combrepeater# # vlog -sv -work work +incdir+D:/1AlteraDsgn/Quart11/0SysVerilog/CombRepeater {D:/1AlteraDsgn/Quart11/0SysVerilog/CombRepeater/CombRepeaterTF.sv}# Model Technology ModelSim ALTERA vlog 6.6d Compiler 2010.11 Nov 2 2010# -- Compiling module CombRepeaterTF# # Top level modules:# CombRepeaterTF#

Modelsim-Altera only supports single-language compilation. Your example is compiling both VHDL and SystemVerilog.

Change your project settings to generate a Verilog netlist (.vo) instead of VHDL netlist (.vho).

Cheers,

Dave

This is the valuable answer, I have changed settings to SystemVerilog and it is working OK.

Thank you! Jaromir