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Altera_Forum
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14 years ago

ModelSim vsim-3039 fatal error

Hi all, I would like to simulate a very simple design in SystemVerilog and to compare the results of RTL and gate level simulation. The RTL simulation works OK but if I launch the gate level s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

dwh,

the full line in question is:

# ** Fatal: (vsim-3039) D:/1AlteraDsgn/Quart11/0SysVerilog/CombRepeater/CombRepeaterTF.sv(5): Instantiation of 'CombRepeater' failed.

It contains the path to my design, I considered it not important.

Jaromir Kolouch