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Altera_Forum
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14 years ago

ModelSim vsim-3039 fatal error

Hi all, I would like to simulate a very simple design in SystemVerilog and to compare the results of RTL and gate level simulation. The RTL simulation works OK but if I launch the gate level s...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Modelsim-Altera only supports single-language compilation. Your example is compiling both VHDL and SystemVerilog.

Change your project settings to generate a Verilog netlist (.vo) instead of VHDL netlist (.vho).

Cheers,

Dave