Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorModelSim vsim-3039 fatal error
Hi all, I would like to simulate a very simple design in SystemVerilog and to compare the results of RTL and gate level simulation. The RTL simulation works OK but if I launch the gate level s...
Altera_ForumHonored Contributor
Honored ContributorModelsim-Altera only supports single-language compilation. Your example is compiling both VHDL and SystemVerilog.
Change your project settings to generate a Verilog netlist (.vo) instead of VHDL netlist (.vho). Cheers, Dave
