Honored ContributorHi,
Im trying to model a buffer in VHDL but am unable to do so. I have signal A and B. I want the first signal A is loaded into a register after 2 seconds. Then, the signal B is generated from the register for the next 2 second. Can anyone help me..Thanks
Honored ContributorIf it is only for simulation, and not synthesis, that is correct dt_conan. This means that the value in register b will be assigned to a with a delay of 1ns. If you are using Verilog, "assign# 10 out = in1" construct can be used. This will delay the assignment 10 units of time, where the unit is defined at the beginning of the file.
Honored ContributorThanks turhank for your response, really help me.
Honored Contributorsure thing =)
Honored ContributorHonored ContributorA stream buffer is useful in cases when the input data is not ready on time (bursty) but output data need to be constant flow.
Very much like flow of water to a tank then released from tank at chosen rate. Example 1: you have module m2 requesting data from module m1 but m1 may lag behind the m2 request one or few clocks. A few stages buffer in between will simplify the interface as data is made available in buffer always. In this case, m1 writes to buffer irrespective of request and m2 reads from buffer when needed. Example 2: you receive bursty video stream but must process it at a given fixed bitrate. You need to store enough bits so that your processing is not interrupted. Standards may also allow you to use null data in case you get short of incoming stream. An important issue here is your buffer’s operating point and its depth… ideally you should work midpoint and let it swing up/down around midpoint. If it gets full you must clear it else you lose the elasticity and suffer loss of data.Honored Contributorunderstand..
tq kaz... can u give the example code for it?Honored ContributorThe subject of discussion (buffer) is not a well circumscribed function or module or IP to write code for. It is built around a fifo and according to what you want to do.
