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Altera_Forum's avatar
Altera_Forum
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15 years ago

model a buffer in VHDL

Hi, Im trying to model a buffer in VHDL but am unable to do so. I have signal A and B. I want the first signal A is loaded into a register after 2 seconds. Then, the signal B is generated ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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what do you mean by buffer? You need to elaborate more.

Buffer is used according to several contexts.

1) I know digitally minded folks use buffer to mean storing incoming streams and then releasing it under control. This could be a block of ram or fifo or even a pipe of registers.

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dear kaz,

mind to elaborate this function?

tqvm in advace...