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Honored Contributor
Honored Contributormodel a buffer in VHDL
Hi, Im trying to model a buffer in VHDL but am unable to do so. I have signal A and B. I want the first signal A is loaded into a register after 2 seconds. Then, the signal B is generated ...
Altera_ForumHonored Contributor
Honored ContributorIf it is only for simulation, and not synthesis, that is correct dt_conan. This means that the value in register b will be assigned to a with a delay of 1ns. If you are using Verilog, "assign# 10 out = in1" construct can be used. This will delay the assignment 10 units of time, where the unit is defined at the beginning of the file.
