Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributormodel a buffer in VHDL
Hi, Im trying to model a buffer in VHDL but am unable to do so. I have signal A and B. I want the first signal A is loaded into a register after 2 seconds. Then, the signal B is generated ...
Altera_ForumHonored Contributor
Honored ContributorThe subject of discussion (buffer) is not a well circumscribed function or module or IP to write code for. It is built around a fifo and according to what you want to do.
