Mobile DDR-SDRAM for Cyclone IV E

I'm afraid that you are a bit out of luck. The Mobile DDR SDRAM specifies the use of DQS for read operation. In contrast with std. DDR2 device the tAC spec is very wide ( 2 to 8 ns in stead of +/- 600 ps) and hence does not allow to use a (fixed or adjustable) clock phase of the PLL to read the incoming data. Even a DLL (as in Cyclone II) will not help because you still need to transfer the captured data into the processing clock domain, and the 'wide' tAC spec doesn't help here.

Indeed, the tAC spec is very wide and complicates the problem here. But there are some expensive mobile DDR IP cores that can run on Cyclone IV E. So there must be a way to get there.

In theory you can train the phase offset of the read clock to capture the data in the middle of the DQS signals. You would have to track it over the Voltage and Temperature variations during operation (as AltmempPHY does). As the capture clock has an undefined phase to the internal process clock, you will need to insert a dcfifo in the read path (as AltmemPHY does ...) adding some latency.

In a DDR/DDR2 controller, I guess that it is only necessary to train the phase offset once as this offset will be quite stable during operation. I guess this is what the ALTMEMPHY is doing during calibration.

The AltmemPHY tracks a 'mimic' clock for variations. I a Mobile design I would try to track the DQS signals. But things get complicated and finally one has to decide: 'build or buy'. Or go back to std DDR2 or perhaps DDR3 (in case of single device there should be little difference, although I haven't studied the DDR3 specs to that depth).

Hello,