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Honored Contributor
Honored ContributorMobile DDR-SDRAM for Cyclone IV E
Hello Guys, I am currently trying to implement a mobile DDR-SDRAM PHY layer for Cyclone IV E. I previously implemented a DDR-SDRAM controller using the ALTMEMPHY with my own controller and it i...
Altera_ForumHonored Contributor
Honored ContributorIn theory you can train the phase offset of the read clock to capture the data in the middle of the DQS signals. You would have to track it over the Voltage and Temperature variations during operation (as AltmempPHY does). As the capture clock has an undefined phase to the internal process clock, you will need to insert a dcfifo in the read path (as AltmemPHY does ...) adding some latency.
I have been dabbling a bit a writing my own PHY for DDR2 and this is already complicated in timing, the training algorithm adds a lot of complexity (in UniPHY Altera even added a NIOS II CPU to do this!). I'm afraid that you're stuck with 'six of the one or half a dozen of the other'
