Mobile DDR-SDRAM for Cyclone IV E

Indeed, the tAC spec is very wide and complicates the problem here. But there are some expensive mobile DDR IP cores that can run on Cyclone IV E. So there must be a way to get there.

Is it possible to calibrate the required delay of DQS for read capture at startup and then keep the same delay for the rest of the time? Or is tAC constantly changing over time?

From what I have seen, the available IP cores seem to be using a fixed delay on DQS. I guess it is just a matter of calibrating then?

thanks,