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Altera_Forum
Honored Contributor
Honored ContributorMobile DDR-SDRAM for Cyclone IV E
Hello Guys, I am currently trying to implement a mobile DDR-SDRAM PHY layer for Cyclone IV E. I previously implemented a DDR-SDRAM controller using the ALTMEMPHY with my own controller and it i...
Altera_ForumHonored Contributor
Honored ContributorIndeed, the tAC spec is very wide and complicates the problem here. But there are some expensive mobile DDR IP cores that can run on Cyclone IV E. So there must be a way to get there.
Is it possible to calibrate the required delay of DQS for read capture at startup and then keep the same delay for the rest of the time? Or is tAC constantly changing over time? From what I have seen, the available IP cores seem to be using a fixed delay on DQS. I guess it is just a matter of calibrating then? thanks,
