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Altera_Forum
Honored Contributor
Honored ContributorMobile DDR-SDRAM for Cyclone IV E
Hello Guys, I am currently trying to implement a mobile DDR-SDRAM PHY layer for Cyclone IV E. I previously implemented a DDR-SDRAM controller using the ALTMEMPHY with my own controller and it i...
Altera_ForumHonored Contributor
Honored ContributorI'm afraid that you are a bit out of luck. The Mobile DDR SDRAM specifies the use of DQS for read operation. In contrast with std. DDR2 device the tAC spec is very wide ( 2 to 8 ns in stead of +/- 600 ps) and hence does not allow to use a (fixed or adjustable) clock phase of the PLL to read the incoming data. Even a DLL (as in Cyclone II) will not help because you still need to transfer the captured data into the processing clock domain, and the 'wide' tAC spec doesn't help here.
