Mixing IO standards on Arria V GX (LVDS / DDR3L SSTL-135)?

Hi,

I am trying to assign FPGA pins for a new Arria V project.

I use 4 hardware DDR3 controllers, 33 LVDS input pins and 1 LVDS output pin in this project.

Quartus fitter compiled but it has mixed different IO standards (LVDS and SSTL-135/differential 1.35-V SSTL) in the same Vref groups and I am not sure that it can works.

I don’t know much about Arria V family and its IO capabilities and I am wondering how do I need to supply FPGA power banks.

If I supply my design with VCCPD=2.5V, VCCIO=1.35V and VREF=1.35V will it work?

Is it possible to mix LVDS inputs and DDR3L IOs in a same Vref group ?

Here are Fitter results:

b3a_n0:

Jtag pins:

- 3 IN / 1 Out, IO standard=2.5V (non assignable pins)

DDR3L pins:

- 1 IN (ddr_rzq), IO standard SSTL-135

- Several Out, IO standard SSTL-135

- 1 Out (ddr_ck), differential 1.35V SSTL

b7a_n0:

LVDS:

- Several LVDS IN

DDR3L pins:

- 1 IN (ddr_rzq), IO standard SSTL-135

b8a_n0:

LVDS

- Several LVDS IN

DDR3L pins:

- 1 IN (ddr_rzq), IO standard SSTL-135

- Several Out, IO standard SSTL-135

- 1 Out (ddr_ck), differential 1.35V SSTL

Thanks in advance for helping.

Environnement:

Quartus 13.0sp1

FPGA Arria V GX 5AGXFA5H4F35C5

4x DDR3L 16bits modules