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Altera_Forum
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12 years ago

Mixing IO standards on Arria V GX (LVDS / DDR3L SSTL-135)?

Hi, I am trying to assign FPGA pins for a new Arria V project. I use 4 hardware DDR3 controllers, 33 LVDS input pins and 1 LVDS output pin in this project. Quartus fitter compiled but it ha...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I had a reply from altera support and the result is:

A bank supply with Vccpd=2.5V / Vccio=1.35V / Vref=0.675V can support:

- LVDS inputs because it use Vccpd voltage only

- SSTL-135 inputs and outputs because all 3 voltages are well set.