migration from EPCQ to EPCQ-A

Hi,

on a custom board we have successfully used an altera Cyclone V (5CEBA2) with an EPCQ32 (ASx4).

Now we had to migrate from the EPCQ32 to the EPCQ32A.

We used Quartus Prime Lite 17.1.0 and 17.1.1 and programmed the EPCQ32A via the Quartus Programmer + USB blaster + SFL.

We followed the migration guideline AN822:

https://www.altera.com/documentation/tfb1498107381358.html

(https://www.altera.com/documentation/tfb1498107381358.html)

After updating the EPCQ in Quartus from EPCQ32 to EPCQ32A, compilation and download of the .jic file to the EPCQ32A are successful, but then the FPGA fails to load the configuration file at startup (CONF_DONE remains low).

We believe the hardware is fine (never had a problem with the EPCQ32).

(MSEL: 10011, nCE to GND, nSTATUS, nCONFIG, CONF_DONE with 10k pull-up to 3V3, six lines between the EPCQ32A and the FPGA (DATA[3..0], nCS, DCLK)

What we noticed in the map file is the following line:

quad-serial configuration device dummy clock cycle: 12

whereas the AN822 states:

--- Quote Start ---

epcq—the dummy clock is configurable with the non-volatile configuration register (nvcr). when the epcq is used with a cyclone® v, arria® v or stratix® v device, the dummy clock is configured to be 4, 10 or 12, depending on the byte-addressing mode and asx1 or asx4 configuration.

however, in epcq-a devices, the dummy clock is fixed at 8 and 6 for fast read and extended quad input fast read respectively. therefore you must regenerate the programming files, such as .pof, .jic, and .rpd.

--- Quote End ---

Is the dummy clock cycle wrong and is it the cause of our problem?

If this is our problem, how can we fix it? (we did not find any place where the dummy clock can be adjusted)

Or is the problem somewhere else? What else can we check?

Thanks for your help,

Regards