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Altera_Forum's avatar
Altera_Forum
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16 years ago

Mem editor in ModelSim Altera edition

Hi,

I know this isn't a ModelSim support forum, but people here probably have an answer.

How to change the order in which words are presented in the ModelSim Altera edition's memory editor? Currently in my installation the order is descending (meaning the beginning of the memory is in the end of the listing). How can I make it ascending and thus more.. ahem.. intuitive? I've seen the editor using ascending order in the tutorial PDF screenshots, so it must be possible to change it. I found properties for changing the radix for both data and address, but nothing for changing the order. Is the setting buried somewhere else or is it somehow implied by the instantiated memory? The user manual doesn't mention anything about this.

Thanks is advance.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Strange but true. I have use two FIFO in my design and in modelsim memory view one will show in descending and other is in ascending order.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    The memories tab in the workspace window also says that the range of the memory is [xxxx:0] instead of [0:xxxx] like in the screenshots of the user manual. So it's probably somehow implied by the instantiation of the memory.

    I'm using altsyncram with these generic mappings: 

    
	altsyncram_component : altsyncram
	GENERIC MAP (
		clock_enable_input_a => "BYPASS",
		clock_enable_output_a => "BYPASS",
		init_file => "",
		intended_device_family => "Cyclone II",
		lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=RAM",
		lpm_type => "altsyncram",
		numwords_a => 2048,
		operation_mode => "SINGLE_PORT",
		outdata_aclr_a => "NONE",
		outdata_reg_a => "UNREGISTERED",
		power_up_uninitialized => "TRUE",
		widthad_a => 11,
		width_a => 8,
		width_byteena_a => 1
	)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Hi

    I observe that when I instantiate memory in verilog code ( reg [7:0] int_mem [0:1024] then modelsim shows memory content in ascending order while memory used in Altera FIFO display in descending order.

    So it look like dependent on memory declaration technique.

    Regards,

    Hardik Sheth