Forum Discussion
5 Replies
- Altera_Forum
Honored Contributor
First what range of periods would you need to measure and second what frequency clocks do you have available?
Assuming your clock is fast enough you can just have a counter than measures the period as a number of clock periods. - Altera_Forum
Honored Contributor
Thanks! and you can for me VHDL code in common! with clock period is 10MHz and range of range of period is from 50 us 5000 us.
- Altera_Forum
Honored Contributor
Here's a basic code template. Signal and port definitions are left up to you.
process (clk) begin if rising_edge(clk) then pulse_inp_sync <= pulse_inp; pulse_inp_prev <= pulse_inp_sync; if (not pulse_inp_prev and pulse_inp_sync ) = '1' then counter <= (others => '0'); period <= counter; elsif counter < MAXCOUNT then counter <= counter + 1; end if; end if; end process; - Altera_Forum
Honored Contributor
Thanks! But you can draw for me timing schematic?
- Altera_Forum
Honored Contributor
Thanks! FvM. I have completed measure period of pulse. And now I have a question: Everyone, Who used DDR2 SDRAM in DSP development Kit Cyclone II Ep2c35F672C6?