Forum Discussion
Altera_Forum
Honored Contributor
17 years agoHere's a basic code template. Signal and port definitions are left up to you.
process (clk)
begin
if rising_edge(clk) then
pulse_inp_sync <= pulse_inp;
pulse_inp_prev <= pulse_inp_sync;
if (not pulse_inp_prev and pulse_inp_sync ) = '1' then
counter <= (others => '0');
period <= counter;
elsif counter < MAXCOUNT then
counter <= counter + 1;
end if;
end if;
end process;