Max/min current to a GPIO

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Please post a schematic/drawing of your proposed interface.

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hi. apologies, i should have added the schematic before.

NPN transistor: NXP BDT125. Max I_c is 6.5mA. Its switching is 2Ghz so it should not give much delay. I will probably add a speed-up capacitor if i need more performance.

X1-40 goes to the GPIO.

My plan:

RB_0=93.5kohm.

RE_0=3.3 kohm

GND is connected to the GND pin of the ATA header and and the V_cc to the 3.3 V pin

I_b comes out to be 0.019 mA. And I_c, comes out to be 0.75 mA.

I can probably change the resistors and and the V_cc to 5V and get I_c to be 3.3 mA, but I rather not if I can get away with it.

my concern was if the GPIO will be sensitive enough to react to the change in voltage at 50ns.

cheers.

PS: i did some additional googling, and I came up with this pdf which states the JEDEC Standard No. 8-5A.01 using by the GPIO and the file has an Absolute maximum continuous rating of as +/- 20 mA. the file also specifies normal operating conditions where It says I_i (Input current) for both high and low as +/-15micro amp.

This is all good. however, if that is specification of JEDEC Standard No. 8-5A.01,, i was hoping someone to confirm that this would work with 0.75mA "source strength". I would hate to make a PCB board only to blow up all the transistors :(

Your level translator won't be very effective. With a 93.5Kohm base resistor even 2pF of capacitance at the base will form a lowpass filter with nearly a 200ns time constant. This will "swallow" your 50ns pulse and produce no output. How much drive current can your detector supply? A simple 3.3V logic gate with a 5V tolerant input might suffice for your level translator.

Having said that I'd like to respond to your initial question; I'd expect the input current of an FPGA I/O pin to be in the uA range, far below the .75mA in your circuit. In any event you won't blow up any transistors if you connect your circuit as drawn.

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Your level translator won't be very effective. With a 93.5Kohm base resistor even 2pF of capacitance at the base will form a lowpass filter with nearly a 200ns time constant. This will "swallow" your 50ns pulse and produce no output. How much drive current can your detector supply? A simple 3.3V logic gate with a 5V tolerant input might suffice for your level translator.

Having said that I'd like to respond to your initial question; I'd expect the input current of an FPGA I/O pin to be in the uA range, far below the .75mA in your circuit. In any event you won't blow up any transistors if you connect your circuit as drawn.

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Yes. I am actually contemplation using a NC7SZ125 (https://www.fairchildsemi.com/datasheets/nc/nc7sz125.pdf)

it has a delay of 3ns, which is not a issue as long as all 16 of these logics have the same delay. This is a concern for me since I will be timestamping them for processing which looks at the time of arrival.

having less uncertainly in this will help me improve statistics and smaller duration of exposure to radioactive stuff :)

but just out of curiosity, I can achieve the same results using R_e=1k and R_b=22K.

and if i using a different transistor ( BFT540) with R_e=50 ohm and R_b=240 ohm.

EDIT: i think it drives 50 mA. which is good for NC7SZ125.