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Your level translator won't be very effective. With a 93.5Kohm base resistor even 2pF of capacitance at the base will form a lowpass filter with nearly a 200ns time constant. This will "swallow" your 50ns pulse and produce no output. How much drive current can your detector supply? A simple 3.3V logic gate with a 5V tolerant input might suffice for your level translator.
Having said that I'd like to respond to your initial question; I'd expect the input current of an FPGA I/O pin to be in the uA range, far below the .75mA in your circuit. In any event you won't blow up any transistors if you connect your circuit as drawn.
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Yes. I am actually contemplation using a NC7SZ125 (
https://www.fairchildsemi.com/datasheets/nc/nc7sz125.pdf)
it has a delay of 3ns, which is not a issue as long as all 16 of these logics have the same delay. This is a concern for me since I will be timestamping them for processing which looks at the time of arrival.
having less uncertainly in this will help me improve statistics and smaller duration of exposure to radioactive stuff :)
but just out of curiosity, I can achieve the same results using R_e=1k and R_b=22K.
and if i using a different transistor ( BFT540) with R_e=50 ohm and R_b=240 ohm.
EDIT: i think it drives 50 mA. which is good for NC7SZ125.
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