Max/min current to a GPIO

Your level translator won't be very effective. With a 93.5Kohm base resistor even 2pF of capacitance at the base will form a lowpass filter with nearly a 200ns time constant. This will "swallow" your 50ns pulse and produce no output. How much drive current can your detector supply? A simple 3.3V logic gate with a 5V tolerant input might suffice for your level translator.

Having said that I'd like to respond to your initial question; I'd expect the input current of an FPGA I/O pin to be in the uA range, far below the .75mA in your circuit. In any event you won't blow up any transistors if you connect your circuit as drawn.